Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. Examples of the different types of buses present in typical computer systems are a system bus to which a host central processing unit is attached and one or more peripheral buses. To permit system-wide communication between devices attached on different buses, bus-to-bus bridges or interfaces are provided to match the communications protocol of one bus with that of another.
Different bus-to-bus bridges are described in the following documents from IBM Corporation: Technical Disclosure Bulletin Vol. 38 No. 5, May 95, pp. 401-402 and EP 0 629 956 A2. These applications describe mechanisms which permit system-wide communication of devices attached to different buses in the system.
Each bus-to-bus bridge in a multi-bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. One such bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time (up to 120 megabytes of data per second). The PCI bus achieves this high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus.
A typical architecture of a communication system which is used to transfer data between an emitter bus to a receiver bus includes a memory within the interface device which temporarily stores data received from the emitter bus before being unloaded to the receiver bus. Interfacing an emitter bus to a receiver bus is problematic when the two buses are asynchronous each other. A write operation performed to input data into the interface circuit is externally monitored by a write clock which is synchronous to the emitter bus clock, whereas a read operation performed to output data from the interface circuit is externally monitored by a read clock which is synchronous to the receiver bus clock.
Moreover to monitor each of the read and write operations inside the memory, a control signal is generated to indicate the status of the memory, e.g. if it is empty or not, and thus allowing or preventing a read or a write operation. If no data are stored thereby meaning that no read operations are to be performed, a flag `empty` is asserted. When data are ready to be output a flag `not-empty` is asserted.
In asynchronous systems wherein the read and write operations are independently clocked, the pulse duration of the flag `not-empty` reflects the data traffic between the two buses. It is, therefore, mandatory that this control signal be accurate to clearly state to the receiver bus when data are available, and thus to perform the data transfer as efficiently as possible.
U.S. Pat. No. 5,506,809 discloses a system for generating such control signal named a status flag with the memory being a First-In- First-Out (FIFO) device. A write pointer indexed synchronously with a write clock signal is counting the available memory space for writing data into the FIFO and is compared to a read pointer indexed synchronously with a read clock signal, which counts the data to be output from the FIFO. The result of such comparison gives the value of the status flag. However, since two asynchronous clocks monitor both the read and the write operations within the FIFO, the status flag duration may be either shorter or longer than the receiver clock cycle, resulting in losing data or in the well-known metastability problem of the receiver system.
One common solution to this problem is to hold the flag pulse during at least one additional cycle whatever the value is (i.e. high level or low level), thereby ensuring that the receiver system has captured the valid level. However, such solutions are time consuming, which is not compliant with the high speed buses architectures, such as the Peripheral Component Interconnect (PCI) bus. Accordingly, it would be desirable to be able to provide a new system which eliminates the aforementioned problems.